1. Technical Field
Disclosed is a synchronous semiconductor memory device. In particular, a circuit and a method for writing data into a synchronous semiconductor memory.
2. Discussion of the Related Art
The operational speed and performance of a synchronous dynamic random access memory SDRAM is improved over a dynamic random access memory (DRAM) when the SDRAM is operated in synchronization with an external system clock and there are frequent sequential data read/write operations.
The operational speed and performance of an SDRAM is further improved when both the rising and falling edges of the system clock is used in reading and writing data, i.e., the clock rate is effectively doubled. This memory device is called the double data rate (DDR) SDRAM. In a DDR SDRAM, a strobe signal, commonly referred to as xe2x80x9cDQSxe2x80x9d, is used in conjunction with the system clock to strobe and clock memory data.
U.S. Pat. No. 6,078,546 to Lee discloses a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. FIG. 1A shows an input circuit disclosed in the ""546 patent which stores a pair of data which is synchronized with either the system clock signal or the data strobe signal. Referring to FIG. 1A, an externally applied data strobe signal DS is received during a data write operation. An edge detector 300 detects an edge of the data strobe signal DS and generates first and second internal strobe signals DS1 and DS2 in synchronization with rising and falling edges of the data strobe signal DS, respectively. The signals DS1 and DS2 are used to strobe the odd and even data into data registers 303A and 303B, respectively. A second edge detector 301 detects an active edge of a system clock. A delay circuit 304 delays the output of the second edge detector 301 and the delayed clock signal CLKD is used to output the data from the data registers to write driver 305.
FIG. 1B shows the structure of the data register 303. Referring to FIG. 1B, the first or the odd data of the pair of data is input first to unit cell R1, where it is strobed by strobe signal DS1 and the complement of DS1. The output of R1 is fed to R2. Unit cell R3 receives the even or the second data bit of the data pair. Unit cells R2 and R3 are both first strobed by a strobe signal DS2 (AWR) and its complement. DS2 (AWR) is a product of the DS2 strobe signal and the write pulse to synchronize the strobe signals to the write operation. The odd and even data pair is then output with clocking by the delayed clock signal CLKD.
FIG. 2 shows a timing diagram of the data write operations of the circuit of FIG. 1A. The timing diagram shows the strobe and clock operations for a 4-bit data string input from DIND. The storage cell R1 stores the odd numbered data D0 and D2 of the data string in synchronism with internal data strobe signals DS1 and its complement/DS1. The storage cell R3 stores the even numbered D1 and D3 in synchronism with strobe signals DS2 and its complement/DS2. The write drivers are activated with the first active external clock signal CLK after the write command WR. Case I illustrates that the data reaches the register circuit 303 with the valid data strobe signals inputted after reference clock signal CLK(0), namely in a case where the value of the t DQSS is maximum. Case II illustrates that data reaches the register circuit 303 with the valid data strobe signals inputted before the reference clock signal CLK(0), namely, in the case where the value of the t DQSS is minimum. The disclosure of U.S. Pat. No. 6,078,546 in its entirety is incorporated by reference herein.
As operational speed of memory devices are further increased, the timing margin between the external system clock and the data strobe signal DS becomes shorter. Accordingly, a need exists for an improved system and method for writing a string of data into a synchronous memory device with increased timing margin.
According to the present invention, a circuit for receiving data for a synchronous semiconductor memory device is provided, comprising: a strobe generator having a flip flop and a plurality of logic gates for generating S(n) internal strobes based on an external strobe signal, each of the S(n) internal strobes having a latch-triggering transition occurring one after another in response to the external strobe signal; a plurality of latches for receiving an n-bit data, including at least one set of latches being clocked by the S(n)th internal strobe and another set of latches for receiving the outputs from the one set of latches, the another set of latches being clocked by an internal clock signal having a period longer than that of an external clock signal and a data write driver for receiving the outputs of the another set of latches and for driving the n-bit data into memory cells of the memory device under clocking control of the external clock.
The circuit further including a frequency divider for dividing by two the external clock signal to derive the internal clock signal for clocking the another set of latches. The plurality of latches includes a first set of L(nxe2x88x921) latches for receiving respective (nxe2x88x921) bits of an n-bit data, each of the first set of latches being clocked by a respective S(nxe2x88x921) internal strobe, and a second set of latches configured to receive respective outputs of the first set L(nxe2x88x921) latches and the nth bit data, the second set of latches being clocked by the S(n)th internal strobe, and a third set of latches for receiving respective outputs of the second set of latches, the third set of latches being clocked by the internal clock signal, the external clock signal being derived from an external memory controller.
Further, the flip flop in the strobe generator is configured as a frequency divider for dividing by two the external strobe signal, and the complementary outputs of the flip flop are applied to the inputs of four AND gates to produce the S(n) internal strobes. Preferably, the semiconductor memory device is a double data rate SDRAM, and wherein (n) is equal to four (4).
A circuit is also provided for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock, wherein the counter is clocked by a first clock derived from the system clock.
Preferably, the first clock is derived from a falling edge of the system clock, and a counter reset signal is generated based on the falling edge of the system clock after a write command, the counter reset signal for resetting the counter. The first set of latches receives the n-bit data serially under clocking control by the internal strobe signal. The second set of latches receives the latched n-bit data in parallel, wherein the indicating signal is output by the counter upon detecting two transitions of the internal strobe signal, and (n) is equal to four.
Accordingly to another aspect of the invention, a circuit for receiving data to be written in a synchronous semiconductor memory device is provided, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of falling edges of an external strobe signal and for outputting a counting signal; an indicating signal generator for receiving the counting signal outputted from the counter and for outputting an indicating signal; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock, wherein the counter is clocked by a first clock derived from the system clock.
Accordingly to still another aspect of the invention, a circuit for receiving data to be written in a synchronous semiconductor memory device is provided, comprising: a first set of latches for receiving an n-bit data upon transition of a first internal strobe signal buffered from a data strobe buffer; a counter for counting the number of rising edges of a second internal strobe signal outputted from the data strobe buffer and for outputting a counting signal; an indicating signal generator for receiving the counting signal outputted from the counter and for outputting an indicating signal; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.
Preferably, a counter reset signal is generated based on the falling edge of the system clock after a write command, the counter reset signal for resetting the counter; and the clock signal is derived by dividing by two the system clock.
A semiconductor memory device is further provided for accessing data in synchronization with an external clock signal, comprising: a converting circuit for outputting at least four bits of serial data as four bits of parallel data in response to a data strobe signal, and a latch circuit for receiving the four bit of parallel data in response to a first clock signal and outputting the four bit of parallel data to a data write circuit in response to the first clock signal, wherein each of the four bits of parallel data has a valid data window corresponding to at least two clock cycles of the external clock signal, wherein the semiconductor memory device further includes a division circuit for dividing an internal clock signal outputted from a clock buffer to output the first clock signal.
According to a further aspect of the present invention, a semiconductor memory device for accessing data in synchronization with rising and falling edges of a clock signal is provided, the semiconductor memory device comprising: a division circuit for generating a second data strobe signal by dividing a first data strobe signal; a plurality of internal strobe signal generating circuits for receiving the first data strobe signal and the second data strobe signal and generating a plurality of internal strobe signals; a plurality of first latch circuits for sequentially latching a plurality of received serial data in synchronization with each of the plurality of internal strobe signals; a second latch circuit for receiving and storing data from the first latch circuit in synchronization with one of the plurality of internal strobe signals; and an output circuit for receiving data from the second latch circuit in response to a predetermined clock signal, and transferring the received data to a data bus line.
The semiconductor memory device further includes: a second division circuit for generating a second clock signal by dividing a first clock signal; and an output circuit for transferring an output signal of the second latch circuit into a data bus line in response to the second clock signal.
A data input circuit for inputting data into a semiconductor memory device is also provided, comprising: a converting circuit for converting serial data into parallel data in synchronization with rising and falling edges of a data strobe signal; a data strobe counter for receiving the data strobe signal and an internal clock signal, for counting the number of pulses of the data strobe signal at an interval where the data strobe signal is enabled, and outputting a count signal corresponding to the number of the pulse signals of the data strobe signal; a first latch circuit for receiving and latching output data of the converting circuit in response to the count signal; and a second latch circuit for receiving and latching output data of the first latch circuit in response to the internal clock signal, wherein the data strobe counter receives a write command signal and is initialized in response to a first transition of the internal clock signal after a valid data strobe signal is input.
Preferably, the data input circuit further includes an indicating signal generating circuit for receiving the count signal and outputting an indicating signal for clocking the first latch circuit, wherein the converting circuit comprises: a third latch circuit for latching odd-numbered data of the serial data in response to the data strobe signal; and a fourth latch circuit for latching even-numbered data of the serial data in response to the data strobe signal, wherein the count signal is generated by counting the number of falling edges of the data strobe signal at the interval where the data strobe signal is enabled.
A data input circuit is also provided, comprising a first register for latching first data input in response to a rising edge of a first pulse signal of a data strobe signal, a second register for receiving and latching output data of the first register in response to a falling edge of the first pulse signal, a third register for receiving and storing output data of the second register in response to a rising edge of a second pulse signal of the data strobe signal, and a fourth register for receiving and storing output data of the third register in response to a falling edge of the second pulse signal; a second latching means comprising a fifth register for latching second data input in response to the falling edge of the first pulse signal of the data strobe signal, a sixth register for receiving and storing output data of the fifth register in response to the rising edge of the second pulse signal of the data strobe signal, and a seventh register for receiving and storing output data of the sixth register in response to the falling edge of the second pulse signal; a third latching means for storing third data input in response to the rising edge of the second pulse signal of the data strobe signal into the third register through the first register and the second register, storing fourth data input in response to the falling edge of the second pulse signal of the data strobe signal into the sixth register through the fifth register, and receiving and storing data from the fourth register of the first latching means in response to an indicating signal generated in response to the falling edge of the second pulse signal of the data strobe signal; a fourth latching means for receiving and storing data stored into the seventh register of the second latching means in response to the indicating signal; a fifth latching means for receiving and storing data stored into the third register of the first latching means in response to the indicating signal; and a sixth latching means receiving and storing data stored into the sixth register of the second latching means in response to the indicating signal.
According to the present invention, a data input method for inputting data in a semiconductor memory device is provided, comprising the steps of: converting N bits of serial data into N bits of parallel data in synchronization with a data strobe signal; transmitting the N bits of parallel data to a first circuit in response to a predetermined signal outputted after the last falling edge of the data strobe signal; and outputting the N bits of parallel data of the first circuit to a second circuit in response to a clock signal derived from an external clock signal, wherein the predetermined signal is derived by counting signal generated from a counter, wherein the clock signal is derived by dividing the external clock signal.